About the project
Proteus is a research project to accelerate the implementation and evaluation of hardware security mechanisms. It consists of two components, an extensible RISC-V CPU and a software ecosystem.
The core
The Proteus core is a RISC-V processor implemented in SpinalHDL. It uses a plugin system that makes the pipeline easy to configure and extend, and features many components relevant to security research, such as a taint tracking mechanism, different speculation and prefetching primitives and their tracking, caches, and a CHERI implementation. The pipeline can be configured either as a classical 5-stage in-order CPU, or as an out-of-order design, making it possible to evaluate extensions in different configurations.
The core was first introduced in the following presentation:
- Marton Bognar, Job Noorman, Frank Piessens. Proteus: An Extensible RISC-V Core for Hardware Extensions. RISC-V Summit Europe, 2023.
Software ecosystem
The software ecosystem repository contains the tools needed to install, run, and evaluate Proteus: a RISC-V GNU toolchain with a Newlib-based board support package, a Verilator simulation flow, formal and functional verification, performance benchmarking, a non-interference-based security evaluation framework, and hardware cost evaluation through EVAL-HD and Xilinx Vivado.
Publications
Papers using the core
- Andrija Nešković, Christian Ewert, Mladen Berekovic, Saleh Mulhem. SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2026.
- Eden Desmet, Suparna Kundu, Ingrid Verbauwhede. Masking Out of Order: Side-Channel Leaks from Software-Masked Cryptography on Out-of-Order Processors and the Impact of Different Clock Frequencies. European Symposium on Research in Computer Security (ESORICS), 2026.
Papers extending the core
- Jens Sprengers, Marton Bognar, Lesly-Ann Daniel, Frank Piessens. SecDMP: Provably Secure Data Memory-Dependent Prefetching. Network and Distributed System Security Symposium (NDSS), 2027.
- Davide Davoli, Marton Bognar, Lesly-Ann Daniel, Benjamin Grégoire, Frank Piessens, Tamara Rezk. dfence: Fine-Grained Speculation Barriers for Efficient and Effective Hardware-Software Protection in the Spectre Era. ACM SIGSAC Conference on Computer and Communications Security (CCS), 2026.
- Jennifer Jackson, Minmin Jiang, David Oswald. CHERI-Crypt: Transparent Memory Encryption on Capability Architectures. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2025.
- Hans Winderix, Marton Bognar, Lesly-Ann Daniel, Frank Piessens. Libra: Architectural Support For Principled, Secure And Efficient Balanced Execution On High-End Processors. ACM SIGSAC Conference on Computer and Communications Security (CCS), 2024. Distinguished Paper Award
- Hans Winderix, Marton Bognar, Job Noorman, Lesly-Ann Daniel, Frank Piessens. Architectural Mimicry: Innovative Instructions to Efficiently Address Control-Flow Leakage in Data-Oblivious Programs. IEEE Symposium on Security and Privacy (S&P), 2024.
- Lesly-Ann Daniel, Marton Bognar, Job Noorman, Sébastien Bardin, Tamara Rezk, Frank Piessens. ProSpeCT: Provably Secure Speculation for the Constant-Time Policy. USENIX Security Symposium, 2023.
- Thomas Van Strydonck, Job Noorman, Jennifer Jackson, Leonardo Alves Dias, Robin Vanderstraeten, David Oswald, Frank Piessens, Dominique Devriese. CHERI-TrEE: Flexible Enclaves on Capability Machines. IEEE European Symposium on Security and Privacy (EuroS&P), 2023.
Master's theses
Proteus has been used and extended in a number of master's theses:
- Rune Verachtert (2025–2026)
- Vincent Penders (2025–2026)
- Robbe Titeca (2025–2026)
- Nik Huybrechts (2025–2026)
- Jens Sprengers (2024–2025)
- Rémy Feyerick (2023–2024)
- Seppe Vanderhallen (2023–2024)
- Robbe Van de Velde (2023–2024)
- Alexander Lescroart (2022–2023)